Figure 1 from A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology | Semantic Scholar
An Introduction to Preemphasis and Equalization in Maxim GMSL SerDes Devices | Analog Devices
The Benefits of Using Linear Equalization in Backplane and Cable Applications
Electronics | Free Full-Text | A Low BER DB-PAM4 Adaptive Equalizer for Large Channel Loss in Wireline Receivers
An Introduction to Preemphasis and Equalization in Maxim GMSL SerDes Devices | Analog Devices
Equalizer circuit used in SerDes macros. | Download Scientific Diagram
Figure 3 from A 6.25Gbps Feed-forward Equalizer in 0.18μm CMOS Technology for SerDes | Semantic Scholar
A tunable, power efficient active inductor-based 20 Gb/s CTLE in SerDes for 5G applications - ScienceDirect
Feedforward Equalizer Location Study for High-Speed Serial Systems | 2019-04-29 | Signal Integrity Journal
PCIe 3.0 Equalization - EDN
An Introduction to Preemphasis and Equalization in Maxim GMSL SerDes Devices | Analog Devices
112G SerDes Modeling And Integration Considerations
ECE 546 Lecture - 27 Equalization
Feedforward Equalizer Location Study for High-Speed Serial Systems | 2019-04-29 | Signal Integrity Journal
Equalization: Manual or Adaptive? | Synopsys - YouTube
HIGH SPEED SERDES (INTRODUCTION) - YouTube
SerDes Design Part 5: Channel Operating Margin, a Powerful Compliance Tool - Electronic Systems Design
PCIe 3.0 Equalization at Transmitter and Receiver | Download Scientific Diagram
CTLE (Continuous Time Linear Equalizer) : HIGH SPEED SERDES - YouTube
SerDes in High-Reliability, Long Reach Systems
An Introduction to Preemphasis and Equalization in Maxim GMSL SerDes Devices | Analog Devices
Overview of SERDES channel equalization techniques
Webinar: Optimize SerDes equalization settings - EDN
112-Gbps LR SerDes PHY Taps CTLE and Time Interleaved Flash ADC to Reduce ADC Resolution - EEWeb
